Arm today has announced Safety Ready Program that is aimed to develop solutions for self-driving cars and has also launched the Cortex-A76AE; its first processor IP designed specifically for autonomous vehicles. The Cortex-A76AE processor comes integrated with redundancy and can compute complex relies on up to 16 Cortex-A76 cores. The Cortex-A76AE can scale to up to 64 cores and has the ability to deliver the aforementioned performance, at high safety integrity. It achieves this through a significant redesign of the Cortex-A76 thus becoming the first high-performance Cortex-A CPU to include the Dual Core Lock-Step (DCLS) and Split-Lock features. The Cortex-A76AE is capable of running in Dual Core Lock-Step (DCLS), and hence is able to contribute towards a system’s ASIL D hardware diagnostic coverage requirements. It comes with memory protection as standard. It supports Single Error Correction, Double Error Detection (SECDED) ECC and Parity protection in the L1 cache, and SECDED ECC protection with the ability to correct in-line, on the L2 and L3 caches. As a part of the Armv8.2 architecture extension, Cortex-A76AE includes RAS features built in. It also includes comparators, which are integrated into the design. The Cortex-A76AE has been developed on an advanced process for the avoidance of systematic faults. This enables it ...
Thursday, 27 September 2018
Arm Cortex-A76AE 7nm ‘autonomous-class’ car processor announced; Safety Ready Program initiative unveiled
Arm today has announced Safety Ready Program that is aimed to develop solutions for self-driving cars and has also launched the Cortex-A76AE; its first processor IP designed specifically for autonomous vehicles. The Cortex-A76AE processor comes integrated with redundancy and can compute complex relies on up to 16 Cortex-A76 cores. The Cortex-A76AE can scale to up to 64 cores and has the ability to deliver the aforementioned performance, at high safety integrity. It achieves this through a significant redesign of the Cortex-A76 thus becoming the first high-performance Cortex-A CPU to include the Dual Core Lock-Step (DCLS) and Split-Lock features. The Cortex-A76AE is capable of running in Dual Core Lock-Step (DCLS), and hence is able to contribute towards a system’s ASIL D hardware diagnostic coverage requirements. It comes with memory protection as standard. It supports Single Error Correction, Double Error Detection (SECDED) ECC and Parity protection in the L1 cache, and SECDED ECC protection with the ability to correct in-line, on the L2 and L3 caches. As a part of the Armv8.2 architecture extension, Cortex-A76AE includes RAS features built in. It also includes comparators, which are integrated into the design. The Cortex-A76AE has been developed on an advanced process for the avoidance of systematic faults. This enables it ...
